In the semiconductor memory industry, there is a technical trend of adopting newer architecture with a larger number of memory banks in order to achieve higher access speed. For example, among synchronous dynamic random-access memories (SDRAM), double data rate two (DDR2) SDRAM may include four memory banks. DDR type three (DDR3) SDRAM may include eight memory banks, DDR fourth generation (DDR4) SDRAM may include sixteen memory banks, and DDR4e may include thirty-two memory banks. Development of processes for fine patterns of semiconductor devices so called 1×-nm technology generation or later has been an important theme in order to keep a small size of the semiconductor devices while having a larger number of memory banks. In the 1×-nm technology processes, increasing costs of the processes have been a critical issue. It is, therefore, important to develop devices in a cost-competitive manner by utilizing existing process technologies. One solution to avoid such cost increase may be reducing areas of peripheral circuits while increasing areas for memory cells.
In recent years, there has been an effort to reduce the areas of the peripheral circuits. For example, Japanese patent application publication H11-203867 (JPA H11-203867) describes a row access control circuit to secure a restore level of memory cell by preventing a selected memory cell from being precharged before a lapse of a minimum row active period (tRAS). In particular, the row access control circuit described in JPA H11-203867 includes a single delay circuit which delays an active command to provide a precharge control signal which is used to keep a row access strobe (RAS) signal at an active level. JPA H11-203867 also describes that the single delay circuit is shared by a plurality of memory banks and the precharge control signal is provided selectively to one of the plurality memory banks to control a precharge operation timing for the one of the plurality memory banks. Thus, the precharge timings for the plurality of memory banks can be individually controlled.